A conventional semiconductor device using self-alignment contact process is first described taking up a dynamic random access memory (DRAM) as an example. FIG. 29 shows a plan view and a cross-sectional view of a conventional DRAM structure. As shown in FIG. 29, in a memory cell of the DRAM, first transfer gates (word lines: WL) are disposed on a semiconductor substrate, and then bit lines (BL) are further placed thereabove. Therefore, a bit line contact is designed between word lines, and dropped into a gap between word lines from above.
On the other hand, with regard to the capacitor, a three-dimensional stack type cell or a trench type cell has been developed instead of the conventional parallel flat plate type electrode that has reached a limit of capacity. In particular, in the stack type, the COB structure (Capacitor-Over-Bit line) is capable of occupying the full area of an unit cell as a memory region, regardless of the bit line contact. Therefore the COB structure has been evaluated again and is being employed increasingly (see for example, IDEM Tech. Dig. 1988, pp. 592-595). In this structure, as suggested by the name COB, the capacitor is located over the bit line. Therefore a contact of the capacitor, i.e., a storage node contact is to be designed inside the lattices formed by the bit lines and word lines, and the contact has to be dropped into a gap between the lattices from above.
With the progress of ultra-fine processing technology, it has become increasingly difficult to control the total variation in overlay or dimension to be smaller than the advancing speed of micronization. If there is any deviation in overlay, the bit line contact or storage node contact may short-circuit with the transfer gate, as shown in FIG. 29, for example. It is therefore required to establish a process assembling technology, or a self-alignment contact technology having a certain margin of controllability in lateral direction in the ultra fine manufacturing process.
FIG. 30 shows an example of self-alignment contact technology using a silicon nitride film. In the technology, there are SiN (silicon nitride) film side wall method and a blanket SiN (silicon nitride) film method. In the SiN (silicon nitride) film side wall method (see U.S. Pat. No. 5,270,240, for example), an upper and side surface of a lead line are covered with a nitride film. In the blanket SiN film method (see Symp. VLSI Tech. Dig. 1987, pp. 93-94, for example), a nitride film is held between interlayer oxide films. In both methods, it is intended to cover a bottom line serving as a transfer gate with a SiN film which functions as an etching stopper. In the SiN side wall method, an oxide film is etched to make a contact with a substrate without cutting through the SiN film. On the other hand, in the blanket SiN method, etching of an oxide film is once stopped at a SiN, and then the SiN and underlying oxide film are etched to make a contact with the substrate.
In such a device having an opening in an oxide layer for self-alignment contact with a nitride film as a stopper, there arises a problem of contact etching for aluminum leads in the later process. FIG. 31 shows various states of aluminum contacts provided through an interlayer insulating film, and indicates that contacts are to be made at various depths in the interlayer film. As shown in FIG. 31, particularly when an interlayer film for the aluminum contact is flattened, the contact becomes deeper in the active region or on the word line, and aspect ratio becomes large. In the fine contact hole with a large aspect ratio, a RIE Lag (reactive ion etching lag) takes place thereby increasing etching speed in the bottom of the hole. Particularly in the self-alignment method employing a nitride film as a stopper, a hard-to-etch nitride film is located on the bottom of the deep contact hole where RIE lag is likely to occur. Therefore, over etching or penetrating may occur in bit line hole or cell plate hole on the upper part, while an opening in the nitride film is being provided in the other deep hole.
Thus, in the conventional manufacturing process of a semiconductor device using self-alignment contacts, various problems exist in the later process of forming an aluminum contact.